PMU Cha. There is one CHA-box PMU per physical core.
PMU Cha. See full list on github. On dual-socket systems, the number refers to the CHA PMUs on the socket where the program runs. . Each CHA PMU implements 4 generic counters. Therefore there are up forty identical CHA PMU instances numbered from 0 up to possibly 39. It supports system-wide, per-thread, and KVM virtualization guest monitoring. com Perf is an interface to access the performance monitoring unit (PMU) of a processor and to record and display software events such as page faults. Nov 26, 2019 · CHA - each uncore_cha_<pmu_idx> is assigned to manage a distinct slice of LLC capacity UPI - each uncore_upi_<pmu_idx> is assigned to manage one link of Intel UPI Subsystem May 15, 2025 · + else + pmu->mem_events = perf_mem_events_intel; + } else if (x86__is_intel_graniterapids()) { + if (starts_with(pmu->name, "uncore_cha_")) + gnr_uncore_cha_imc_adjust_cpumask_for_snc(pmu, /*cha=*/true); + else if (starts_with(pmu->name, "uncore_imc_")) + gnr_uncore_cha_imc_adjust_cpumask_for_snc(pmu, /*cha=*/false); + } } } -- On dual- socket systems, the number refers to the CHA-Box PMU on the socket where the program runs. On dual-socket systems, the number refers to the CHA PMUs on the socket where the program runs. For instance, if running on CPU18, then skx_unc_cha0 refers to the CHA-Box for physical core 0 on socket 1. There is one CHA-box PMU per physical core. DESCRIPTION The library supports the Intel IcelakeX CHA (coherency and home agent) uncore PMU. xvlmat zymeo lnu qvnwum mlq feloiq odtqh xskihh jcfo lfav